Static random access memories (SRAMs) have memory cells which are more effectively read when the bit line pairs to which they are coupled are precharged to some predetermined voltage. A technique that is often used to accomplish this precharge is to equalize the voltage on the bit lines in response to a an address transition. The voltage generally chosen as the precharge voltage is equal to one N channel threshold voltage below the positive power supply voltage. During the writing of the memory cells, one of the bit lines of the bit lien pairs is at a voltage near the positive power supply and the other is at ground potential. To charge bit lines after a write cycle requires that the capacitance of the bit lines be quickly charged for rapid access of a memory cell.
The charging of the bit lines consequently requires a relatively large amount of current even though it is for a relatively short period of time. The peak current requirement is thus much greater than the average current. A power supply for the memory must not only be able to handle the average current requirement but the peak current requirement as well. When the peak current requirement is significantly greater than the average current requirement, the primary size and cost of the power supply may be controlled by the peak current requirement. Additionally, high peak currents cause voltage spikes in the power supply bus on which many other devices are also connected. As seen by other devices as well as the internal circuitry of the memory causing the spike, the spike is noise which can cause operating problems. Thus the desirabilty of rapid precharging of the bit lines is in conflict with the desirabilty of minimal peak currents.